Ferroelectric memory cells and microcontrollers which contain ferroelectric memory portions are currently being manufactured or considered for high volume production. When manufacturing PMOS and/or NMOS transistors on a semiconductor substrate, the PMOS and/or NMOS transistors are usually exposed to a hydrogen anneal process. This hydrogen anneal process neutralizes dangling bonds and reduces surface charge problems at the substrate-to-gate-oxide interface of the PMOS and/or NMOS transistors. Therefore, the hydrogen anneal greatly enhances transistor yield, where electrical breakdown of gate dielectrics are reduced and threshold voltage (Vt) shifts are minimized. However, the hydrogen anneal process incorporates hydrogen into the substrate and this hydrogen anneal is damaging to the deposited ferroelectric material. Therefore, when integrating NMOS and/or PMOS transistors onto an integrated circuit substrate along with ferroelectric capacitors, a hydrogen anneal may be used to improve the yield of CMOS transistors, however, this anneal process creates a yield reduction in the ferroelectric capacitors which overlie the CMOS transistors. The total yield of the IC is probably not significantly improved by the hydrogen anneal and the yield may even be reduced when using a conventional transistor hydrogen anneal methodology due to increased ferroelectric failure rates.
Instead of performing a hydrogen anneal, an oxygen anneal may be used to improve the yield of ferroelectric capacitors. However, an oxygen anneal can typically damage underlying PMOS and NMOS transistors. Therefore, if hydrogen anneal processes are used as known in the prior art, CMOS transistors in the substrate are improved in yield while ferroelectric capacitors overlying the transistors are damaged. In the alternative, when using an oxygen anneal, the ferroelectric capacitors are improved in yield while the transistors within the substrate are either damaged or not properly annealed to remove transistor process damage so that the yield of the transistors are inadequate. Therefore, there is no method in the prior art for annealing both ferroelectric and transistor devices on a single integrated circuit substrate to enhance the yield of both the ferroelectric capacitors and the yield of the transistors simultaneously to enhance overall IC yield. The need exists, in order to reduce costs and provide a better manufactured integrated circuit, to provide an annealing methodology which allows for high yield ferroelectric capacitors to be integrated with high yield PMOS and NMOS transistors in a single process flow.